Start with your chip design.

Getting started

1. Request private beta access with your design goal, PDK, and operating system.
2. Confirm your desktop or hosted trial setup with the team. Current development and hosted trial environments use Linux; ask about availability for other systems.
3. Start with an example circuit. Open the schematic workspace, inspect device parameters, and run its simulation before adapting it to your own design.

The design workspace runs as a desktop application. Hosted trials provide remote access by arrangement. AI services require a network connection and the account configuration supplied during onboarding.

Supported PDKs

Synthetic CMOS

The bundled generic_cmos kit is for examples, exploration, and testing. It is not a manufacturing process.

Bring-your-own gpdk045

An import path exists for user-supplied, licensed gpdk045 installations. Device models, layout rules, and extraction setup need to be checked for the intended workflow. Licensed kit files are not bundled.

Other process kits

For SKY130, GF180, IHP, or a foundry kit, send the process name and required analyses when requesting access. Compatibility and verification coverage must be confirmed; these kits are not advertised as validated out of the box.

Simulation

1. Open or create a schematic and check its models, supplies, stimulus, and ground connections.
2. Select the analysis for your question: DC for operating points and sweeps, AC for small-signal response, or transient for time-domain behavior.
3. Run the configured testbench and inspect the resulting waveforms. Check the run status before interpreting a plot.
4. Change a parameter and rerun. Preserve the circuit, analysis settings, and result together so comparisons remain meaningful.

Available analyses depend on the configured simulator and build. The recorded product demos show the simulation interface and assistant analysis.

Visual AI and the design assistant

Aluming combines specialized visual models with design tools and simulation feedback to automate manual work in analog chip design. The initial focus is inspection and repair: recognizing layout layers, interpreting simulation plots, and helping engineers evaluate changes.

Available visual models and automation tasks depend on your beta build and setup; confirm the workflow you want to automate during onboarding.

Give the assistant a concrete chip-design task and a target to check. For example: “Review this inverter’s transient response and explain the rise and fall times.” Inspect proposed changes, then use simulation and verification to evaluate them.

AI output needs engineering review. Confirm the selected model, account, and data-sharing setup before using proprietary designs. Private beta onboarding covers the available agent tools and approval settings.

Layout and verification

Inspect layers and connectivity in the layout editor, run the configured design-rule checks (DRC), and compare layout against schematic (LVS). Extraction and post-layout simulation depend on the process setup.

The inverter walkthrough demonstrates schematic, simulation, layout, DRC, LVS, and GDS export. A passing demo is evidence for that example and configuration, not foundry signoff qualification.

Scripting and reproducibility

Aluming uses command-based tools and scripted engineering workflows. Ask the team for the supported commands and automation entry points for your beta build; a stable public API reference is not yet available.

Keep text schematics, netlists, and scripts in your own Git repository. Record model and PDK versions, analysis settings, and tool versions beside each result. This describes an external version-control workflow, rather than a built-in Git client.

FAQ